An Area-Efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets

Author

Yamamoto, Ryosuke ; Hamanaka, Chikara ; Furuta, Jun ; Kobayashi, Kazutoshi ; Onodera, Hidetoshi

Author_Institution

Grad. Sch. of Sci. & Technol., Kyoto Inst. of Technol., Kyoto, Japan

Volume

58

Issue

6

fYear

2011

Firstpage

3053

Lastpage

3059

Abstract

A layout structure to avoid upsets due to Multiple Cell Upsets (MCUs) is proposed for rad-hard dual-modular Flip-Flops (FFs) called BCDMR (Bistable Cross-coupled Dual-Modular Redundancy) by separating critical components. We have fabricated a 65 nm chip including 30 kbit dual-modular FF arrays on twin-well and triple-well structures. High-energy broad-spectrum neutron irradiations reveal that no soft error is observed up to 100 MHz in the twin-well, but some errors are observed in the triple well. The triple-well structure is sensitive to MCUs because the p-well potential can be easily elevated.

Keywords

CMOS logic circuits; error statistics; flip-flops; neutron effects; radiation hardening (electronics); area-efficient radiation-hard dual-modular flip-flop; bistable cross-coupled dual-modular redundancy; critical components; dual-modular flip-flop arrays; high-energy broad-spectrum neutron irradiations; layout structure; multiple cell upsets; p-well potential; size 65 nm; soft error; triple-well structure; twin-well structure; CMOS technology; Flip-flops; Layout; Radiation hardening; Single event upset; 65 nm bulk CMOS; bi-stable cross-coupled dual-modular (BCDMR); built-in soft-error resilience (BISER); dual-interlocked storage cell (DICE); flip-flop; multiple cell upset (MCU); radiation-hard design;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2011.2169457

Filename

6093866