Parallel implementation of motion-compensation for HDTV video decoder

Author

Lee, Charng L.

Author_Institution

Comut. & Commun. Res. Labs., Ind. Technol. Res. Inst., Chutung, Taiwan

Volume

44

Issue

2

fYear

1998

fDate

5/1/1998 12:00:00 AM

Firstpage

251

Lastpage

255

Abstract

A parallel motion compensation architecture is proposed for an HDTV video decoder. It is based on block layer picture partitioning. It adds a routing module between decoding engines and block layer memory modules. It can resolve memory access conflicts and avoid extra access delay. The simultaneous access and identical addressing properties make the control scheme very simple. The routing network can be implemented by a simple interconnection network. This architecture is applicable to macroblock structures of 4:2:0, 4:2:2 and 4:4:4 chroma formats. This architecture can be one of the solutions for a parallel HDTV video decoder

Keywords

decoding; high definition television; motion compensation; multiprocessor interconnection networks; parallel architectures; telecommunication network routing; television standards; video equipment; video signal processing; HDTV video decoder; access delay; access properties; addressing properties; architecture; block layer memory modules; block layer picture partitioning; chroma formats; control scheme; decoding engines; interconnection network; macroblock structures; memory access conflicts; motion-compensation; parallel implementation; routing module; routing network; Concurrent computing; Decoding; Delay; Discrete cosine transforms; HDTV; Motion compensation; Parallel processing; Routing; Transform coding; Video compression;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.681934

Filename

681934