Low-power explicit-pulsed triggered flip-flop with robust output

A novel power-efficient explicit-pulsed dual-edge triggered flip-flop (SEDNIFF) is proposed. The proposed SEDNIFF puts the latch node inside its structure, which not only simplifies the latch structure but also strengthens the robustness of the output signal. Based on the TSMC0.18 μm technology, the post-layout simulation results show that the proposed flip-flop gains an improvement of up to 17.9 and 23.5% in terms of total average power and power-delay product, respectively, as compared with its counterparts.