Design Requirements for Steeply Switching Logic Devices

Many steeply switching logic devices have recently been proposed to overcome the energy efficiency limitations of CMOS technology. In this paper, circuit-level energy-performance analysis is used to derive the design requirements for these alternative switching devices. Using a simple analytical approach, this paper shows that the optimal I_on/I_off and E_dyn/E_leak ratios are set only by circuit-level parameters as well as the device transfer characteristic off-state S_off, on -state S_on, and effective S_eff inverse slopes. For a wide variety of switching device characteristics and circuit parameters, the optimal E_dyn/E_leak ratio is approximately (K/2)(S_eff/S_off) - 0.56(S_on/S_off) - 0.56, where K ranges from 6.23 to 11.9. Based upon this theoretical framework, simple requirements for S_off, S_on, and S_eff are established in order for an alternative switching device to be more energy efficient than a MOSFET. The results reemphasize that merely focusing on achieving the steepest local inverse slope S is insufficient, since energy dissipation is set mainly by S_eff and not by S. Finally, the general shape of the energy-delay curve is also set by these inverse slopes, with its steepness directly proportional to S_on/S_off. This analytical approach provides a simple method to assess the promise of any new device technology in potentially overcoming the energy efficiency limitations of CMOS technology.