A parallel processing chip with embedded DRAM macros

Author

Sunaga, Toshio ; Miyatake, Hisatada ; Kitamura, Koji ; Kogge, Peter M. ; Retter, Eric

Author_Institution

Yasu Technol. Application Lab., IBM Japan Ltd., Shiga, Japan

Volume

31

Issue

10

fYear

1996

fDate

10/1/1996 12:00:00 AM

Firstpage

1556

Lastpage

1559

Abstract

A combined DRAM and logic chip has been developed for massively parallel processing (MPP) applications. A trench cell 4-Mb CMOS DRAM technology is used to fabricate the chip with an additional third-level metal layer. The 5-V 0.8-μm technology merges 100-K gate custom logic circuits and 4.5-Mb DRAM onto a 14.7×14.7 mm² die. The DRAM design is based on a 32-K×9-b (288-Kb) self-consistent macro form. It has independent address inputs, data I/O ports, access control circuits, and redundancy fuses and elements. The logic part of the chip consists of eight 16-b CPUs and some broadcast logic circuits. Each CPU and two DRAM macros (64-KB) comprise a processing element (PE), and hypercube connections among eight PE´s are made for the scalable MPP capability. Each chip delivers 50-MIPS of performance at 2.7 W

Keywords

CMOS digital integrated circuits; DRAM chips; hypercube networks; microprocessor chips; parallel architectures; redundancy; 0.8 micron; 16 bit; 2.7 W; 4.5 Mbit; 5 V; 50 MIPS; access control circuits; combined DRAM/logic chip; data I/O ports; embedded DRAM macros; hypercube connections; independent address inputs; massively parallel processing applications; parallel processing chip; redundancy fuses; trench cell CMOS DRAM technology; Access control; Broadcasting; CMOS logic circuits; CMOS technology; Central Processing Unit; Fuses; Hypercubes; Logic circuits; Parallel processing; Random access memory;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.540068

Filename

540068