Combining trace sampling with single pass methods for efficient cache simulation

Author

Conte, Thomas M. ; Hirsch, Mary Ann ; Hwu, Wen Mei W

Author_Institution

Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA

Volume

47

Issue

6

fYear

1998

fDate

6/1/1998 12:00:00 AM

Firstpage

714

Lastpage

720

Abstract

The design of the memory hierarchy is crucial to the performance of high performance computer systems. The incorporation of multiple levels of caches into the memory hierarchy is known to increase the performance of high end machines, but the development of architectural prototypes of various memory hierarchy designs is costly and time consuming. In this paper, we will describe a single pass method used in combination with trace sampling techniques to produce a fast and accurate approach for simulating multiple sizes of caches simultaneously

Keywords

cache storage; discrete event simulation; parallel architectures; performance evaluation; architectural prototypes; cache simulation; high end machines; high performance computer systems; memory hierarchy; performance; single pass method; single pass methods; trace sampling; Algorithm design and analysis; Analytical models; Computational modeling; Computer architecture; Computer simulation; High performance computing; Investments; Prototypes; Sampling methods; Stacking;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.689650

Filename

689650