DocumentCode
140
Title
TDDB Monitoring and Compensation Circuit Design for Deeply Scaled CMOS Technology
Author
Haiqing Nan ; Kyuwon Choi
Author_Institution
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
Volume
13
Issue
1
fYear
2013
fDate
Mar-13
Firstpage
18
Lastpage
25
Abstract
In this paper, a time-dependent dielectric breakdown (TDDB) compensation method with two TDDB monitoring circuits for reliable designs is proposed in 32-nm CMOS technology. To the best of our knowledge, there is no TDDB compensation method or TDDB monitoring circuits proposed before. The proposed TDDB monitoring circuits are referred to as soft breakdown (SBD) monitoring circuit and hard breakdown (HBD) monitoring circuit, which generate a fixed output pattern when severe SBD or HBD occurs. Based on the output of the monitoring circuits, the TDDB compensation method is proposed to completely overcome severe performance degradation and functionality failure due to SBD and HBD. The effectiveness and design costs of the proposed designs are evaluated using ISCAS´85 benchmark circuits.
Keywords
CMOS integrated circuits; compensation; electric breakdown; integrated circuit design; integrated circuit reliability; ISCAS´85 benchmark circuits; TDDB monitoring circuits; compensation circuit design; deeply scaled CMOS technology; fixed output pattern; hard breakdown monitoring circuit; size 32 nm; soft breakdown monitoring circuit; time-dependent dielectric breakdown; Electric breakdown; Inverters; Logic gates; Monitoring; Resistors; Ring oscillators; Stress; Circuit reliability; TDDB compensation; monitoring circuit; time-dependent dielectric breakdown (TDDB); triple modular redundancy (TMR);
fLanguage
English
Journal_Title
Device and Materials Reliability, IEEE Transactions on
Publisher
ieee
ISSN
1530-4388
Type
jour
DOI
10.1109/TDMR.2011.2167624
Filename
6016215
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