Via hole technology for thin-film transistor circuits

Author

Gleskova, H. ; Wagner, S. ; Zhang, Q. ; Shen, D.S.

Author_Institution

Dept. of Electr. Eng., Princeton Univ., NJ, USA

Volume

18

Issue

11

fYear

1997

Firstpage

523

Lastpage

525

Abstract

We analyze and demonstrate a new technique for reducing the gate RC delay of the amorphous silicon thin-film transistor (TFT) backplane of active matrix liquid crystal displays. The TFT gate line is driven from a bus on the back side of the glass substrate, through a laser-drilled via hole. Analysis shows that a few via holes suffice to considerably reduce the gate RC delay, or enable an equivalent increase in display size.

Keywords

amorphous semiconductors; delays; elemental semiconductors; field effect transistor circuits; hydrogen; large screen displays; laser beam machining; liquid crystal displays; semiconductor device metallisation; silicon; thin film transistors; AMLCD; Si:H; TFT gate line; a-Si:H TFT backplane; active matrix liquid crystal displays; display size increase; gate RC delay reduction; glass substrate; large-area displays; laser-drilled via hole; thin-film transistor circuits; via hole technology; Active matrix liquid crystal displays; Active matrix technology; Amorphous silicon; Backplanes; Circuit analysis; Delay; Glass; Liquid crystal displays; Substrates; Thin film transistors;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.641433

Filename

641433