A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders

Author

Goto, Gensuke ; Inoue, Atsuki ; Ohe, Ryoichi ; Kashiwakura, Shoichiro ; Mitarai, Shin ; Tsuru, Takayuki ; Izawa, Tetsuo

Author_Institution

Syst. LSI Dev. Labs., Fujitsu Labs. Ltd., Kawasaki, Japan

Volume

32

Issue

11

fYear

1997

fDate

11/1/1997 12:00:00 AM

Firstpage

1676

Lastpage

1682

Abstract

A 54×54-b multiplier with only 60 K transistors has been fabricated by 0.25-μm CMOS technology. To reduce the total transistor count, we have developed two new approaches: sign-select Booth encoding and 48-transistor 4-2 compressor circuits both implemented with pass transistor logic. The sign-select Booth algorithm simplifies the Booth selector circuit and enables us to reduce the transistor count by 45% as compared with that of the conventional one. The new compressor reduces the count by 20% without speed degradation. By using these new circuits, the total transistor count of the multiplier is reduced by 24%. The active size of the 54×54-b multiplier is 1.04×1.27 mm and the multiplication time is 4.1 ns at a 2.5-V power supply

Keywords

CMOS logic circuits; digital arithmetic; encoding; multiplying circuits; 0.25 micron; 2.5 V; 4-2 compressor circuits; 4.1 ns; 54 bit; Booth selector circuit; CMOS technology; compact 54×54-b multiplier; pass transistor logic; sign-select Booth algorithm; sign-select Booth encoders; Adders; Application software; CMOS technology; Circuits; Computer graphics; Data processing; Encoding; Laboratories; Large scale integration; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.641687

Filename

641687