A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand"

A 1.3-cycle lock-in time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation is proposed with an array structure of short-circuit-current-suppression interpolators. The circuits have been fabricated with a 0.25-/spl mu/m digital CMOS and operated in any condition where digital CMOS circuits operate. Measured results have achieved 1.3 clock cycle lock time and cycle-to-cycle jitter suppression characteristics. The circuits have been verified in 622-Mb/s clock and data recovery that satisfied the ITU-T G.958 jitter tolerance specification.