A 3.3-V power adaptive 1244/622/155 Mbit/s transceiver for ATM, SONET/SDH

This paper presents the implementation of a multirate 155-, 622-, or 1244-Mbit/s transceiver for ATM and SDH/SONET in a 0.5-μm BiCMOS. The internal high-speed clock generation is based on PLL´s with 1.24-GHz VCO´s. The solutions presented here allow us to get rid of the external trimming of the free-running frequency of VCO. The automatic adjustment of the clock and data recovery PLL VCO free running is performed, and thus, increases the robustness of the RX function without expenses in manual trimming. The architecture of this transceiver is thought to enable the full-frequency Wafer test of the whole core by specific loop-back modes. As the same core is used for 155-Mbit/s, 622-Mbit/s, and 1.2-Gbit/s power adaptation techniques are implemented which lead to a 660-mW consumption for 155-Mbit/s operation and 1.1 W for 1.24 Gbits/s. A specific digitally programmable power adaptive ECL cell library concept is presented. Noise precautions are also described, as well as an analog HDL top-down methodology developed by SGS-Thomson Central R&D to short-down the development time and increase reusability