A 15-b resolution 2-MHz Nyquist rate ΔΣ ADC in a 1-μm CMOS technology

Author

Marques, Augusto Manuel ; Peluso, Vincenzo ; Steyaert, Michel S J ; Sansen, Willy

Author_Institution

ESAT, Katholieke Univ., Leuven, Heverlee, Belgium

Volume

33

Issue

7

fYear

1998

fDate

7/1/1998 12:00:00 AM

Firstpage

1065

Lastpage

1075

Abstract

A high-resolution high-speed fourth-order cascaded ΔΣ analog-to-digital converter, based on a 2-1-1 topology, is presented. The converter is implemented with fully differential switched capacitor circuits in a standard 1-μm CMOS technology. The converter uses two symmetrical reference voltages of 1 V, and is driven by a single 48-MHz clock signal. With an oversampling ratio of only 24, the converter achieves a resolution of 91 dB, a peak SNR of 90 dB, and a peak SNDR of 85 dB at a Nyquist rate of 2 MHz after comb filtering. The power consumption of the converter is 230 mW, from a single 5-V supply voltage

Keywords

CMOS integrated circuits; Nyquist criterion; sigma-delta modulation; switched capacitor networks; ΔΣ ADC; 1 micron; 15 bit; 2 MHz; 2-1-1 topology; 230 mW; 48 MHz; 5 V; CMOS technology; Nyquist rate; comb filtering; fully differential switched capacitor circuits; oversampling ratio; peak SNDR; peak SNR; power consumption; resolution; symmetrical reference voltages; Analog-digital conversion; CMOS technology; Circuit topology; Clocks; Energy consumption; Filtering; Signal resolution; Switched capacitor circuits; Switching converters; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.701262

Filename

701262