Design of high performance double edge-triggered flip-flops

A methodology for constructing double edge-triggered flip-flops (DETFFs) from existing latches, which removes the need for complete flip-flops or the presence of clocked nodes in the combining section is presented. The application of this methodology to designing DETFFs based on latches constructed from pass transistor/transmission gates, true single-phase clocked structures, and differential logic is investigated. The resulting DETFFs deliver high performance and do not suffer from the problems of charge sharing, charge coupling, reduced voltage swing, poor supply voltage scaling properties, and excessive power dissipation plaguing existing DETFFs