VLSI implementation of 2-D discrete wavelet transform for real-time video signal processing

Author

Yu, Chu ; Chen, Sao-Jie

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

43

Issue

4

fYear

1997

fDate

11/1/1997 12:00:00 AM

Firstpage

1270

Lastpage

1279

Abstract

This paper presents the architecture and implementation of a single-chip VLSI for the two-dimensional discrete wavelet transform (2-D DWT) decomposition. This nonseparable based architecture uses a parallel-systolic filter structure to compute all the resolution levels of the DWTs, such that the input samples can be processed at the rate of one sample per clock cycle. The chip was fabricated in a 0.6 μm CMOS technology and packaged as a 48-pin DIP. For the computation of an N×N still image with a filter length L, this chip needs N²+N clock cycles and N(2L-1) memory storage; for continuous picture such as video signal, its average computation time per picture is about N² only

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; image sampling; parallel architectures; transforms; two-dimensional digital filters; video signal processing; wavelet transforms; 0.6 micron; 2D DWT decomposition; 2D discrete wavelet transform; 48-pin DIP; CMOS technology; VLSI implementation; average computation time; clock cycle; filter length; input samples; memory storage; nonseparable based architecture; parallel-systolic filter structure; real-time video signal processing; resolution levels; single-chip VLSI architecture; still image computation; CMOS technology; Clocks; Computer architecture; Concurrent computing; Discrete wavelet transforms; Filters; Image storage; Packaging; Two dimensional displays; Very large scale integration;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.642396

Filename

642396