DocumentCode
1405601
Title
Interblock memory for turbo coding
Author
Yeh, Chia-Jung ; Ueng, Yeong-Luh ; Lin, Mao-Chao ; Lu, Ming-Che
Author_Institution
Grad. Inst. of Commun. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
58
Issue
2
fYear
2010
fDate
2/1/2010 12:00:00 AM
Firstpage
390
Lastpage
393
Abstract
We investigate a binary code, which is implemented by serially concatenating a multiplexer, a multilevel delay processor, and a signal mapper to a binary turbo encoder. To achieve improved convergence behavior, we modify the binary code by passing only a fraction of the bits in the turbo code through the multilevel delay processor and the signal mapper. Two decoding methods are discussed and their performances are evaluated.
Keywords
binary codes; turbo codes; binary code; binary turbo encoder; convergence behavior; interblock memory; multilevel delay processor; multiplexer; signal mapper; turbo coding; Binary codes; Block codes; Concatenated codes; Convergence; Delay; Iterative decoding; Multiplexing; Performance evaluation; Signal mapping; Turbo codes; Turbo codes, concatenated codes, binary codes;
fLanguage
English
Journal_Title
Communications, IEEE Transactions on
Publisher
ieee
ISSN
0090-6778
Type
jour
DOI
10.1109/TCOMM.2010.02.060534
Filename
5407597
Link To Document