An energy-efficient noise-tolerant dynamic circuit technique

Noise in deep submicron technology combined with the move toward dynamic circuit techniques have raised concerns about reliability and energy efficiency of VLSI systems in the deep submicron era. To address this problem, a new noise-tolerant dynamic circuit technique is presented. The average noise threshold energy (ANTE) and the energy normalized ANTE (NANTE) metrics are proposed to quantify the noise immunity and energy efficiency, respectively. Simulation results in 0.35-μm CMOS for NAND gate and full-adder designs indicate that the proposed technique improves the ANTE and NANTE by 2× and 1.4× over conventional domino circuits. The improvement in the NANTE is 11% higher than the existing noise-tolerance techniques. Furthermore, the proposed technique has a smaller area overhead (36%) as compared to static circuits whose area overhead is 60%. Also presented in this paper is an ASIC developed in 0.35-μm CMOS to evaluate the performance of the proposed technique. Experimental results demonstrate a 27% average improvement in noise immunity over conventional dynamic circuits.