A multipage cell architecture for high-speed programming multilevel NAND flash memories

Author

Takeuchi, Ken ; Tanaka, Tomoharu ; Tanzawa, Toru

Author_Institution

Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan

Volume

33

Issue

8

fYear

1998

fDate

8/1/1998 12:00:00 AM

Firstpage

1228

Lastpage

1238

Abstract

To realize low-cost, highly reliable, high-speed programming, and high-density multilevel flash memories, a multipage cell architecture has been proposed. This architecture enables both precise control of the V_th of a memory cell and fast programming without any area penalty. In the case of a four-level cell, a high programming speed of 236 μs/512 bytes or 2.2 Mbytes/s can be obtained, which is 2.3 times faster than the conventional method. A small die size can be achieved with the newly developed compact four-level column latch circuit. A preferential page select method has also been proposed so as to improve the data retention characteristics. The IC error rate can be decreased by as much as 33%, and a highly reliable operation can be realized

Keywords

EPROM; NAND circuits; PLD programming; integrated circuit reliability; integrated memory circuits; memory architecture; 2.2 Mbyte/s; data retention characteristics; error rate reduction; four-level cell; four-level column latch circuit; high reliability; high-density memories; high-speed programming; highly reliable operation; low-cost memory; multilevel NAND flash memories; multipage cell architecture; preferential page select method; Circuits; Costs; Degradation; Energy consumption; Error analysis; Flash memory; Latches; Threshold voltage; Tunneling; Voltage control;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.705361

Filename

705361