A cost-effective three-step hierarchical search block-matching chip for motion estimation

Author

Chen, Thou-Ho

Author_Institution

Dept. of Electron. Eng., Nan-Tai Inst. of Technol., Tainan, Taiwan

Volume

33

Issue

8

fYear

1998

fDate

8/1/1998 12:00:00 AM

Firstpage

1253

Lastpage

1258

Abstract

A dedicated cost-effective chip of a three-step hierarchical search (3SHS) motion estimator to support the NTSC resolution video in real time is proposed. The memory interleaving technique is developed to overcome the 3SHS´s inherent problem of complicated data addressing and interconnection due to the variable distance between candidate locations and unpredictable data requirements. Based on a cyclic-pipeline utilization of memory, the memory size and bandwidth requirements can be reduced significantly. With 0.8 μm CMOS technology, the proposed chip requires a die size of 6.9×5.9 mm² with 120 K transistors, and is able to operate at a clock rate of more than 50 MHz

Keywords

CMOS digital integrated circuits; digital signal processing chips; image matching; motion estimation; search problems; 0.8 micron; 3SHS; 50 MHz; CMOS chip; NTSC resolution video; bandwidth; block matching algorithm; cyclic-pipeline architecture; data addressing; interconnection; memory interleaving; motion estimation; real time; three-step hierarchical search; Bandwidth; CMOS technology; Clocks; HDTV; Helium; Integrated circuit interconnections; Interleaved codes; Motion estimation; Pipelines; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.705365

Filename

705365