DocumentCode
1410065
Title
Prolog To Defect Tolerance In Vlsi Circuits: Techniques And Yield Analysis
Author
Falk, Howard
Volume
86
Issue
9
fYear
1998
Firstpage
1817
Lastpage
1818
Keywords
Chip scale packaging; Circuit faults; Circuit synthesis; Integrated circuit yield; Microprocessors; Programmable logic arrays; Prototypes; Pulp manufacturing; Redundancy; Very large scale integration;
fLanguage
English
Journal_Title
Proceedings of the IEEE
Publisher
ieee
ISSN
0018-9219
Type
jour
DOI
10.1109/JPROC.1998.705524
Filename
705524
Link To Document