DocumentCode
1411050
Title
A shallow trench isolation using nitric oxide (NO)-annealed wall oxide to suppress inverse narrow width effect
Author
Kim, Jongoh ; Kim, Taewoo ; Park, Jaebeom ; Kim, Woojin ; Hong, Byungseop ; Yoon, Gyuhan
Author_Institution
Device & Process Integration Part, Hyundai Electron. Ind. Co. Ltd., Kyoungki, South Korea
Volume
21
Issue
12
fYear
2000
Firstpage
575
Lastpage
577
Abstract
A simple method to suppress INWE of transistor based on STI technology has been demonstrated in this paper. In order to prevent the boron out-diffusion through the trench sidewall, the nitric oxide (NO)-annealed wall oxidation is performed before the gap-filling process. By reviewing the electrical properties of n- and p-MOSTs, it has been confirmed that INWE of n-MOST can be easily suppressed without any problem in p-MOST, and the uniformity of parameter can be remarkably improved by this method. Also, the gate oxide integrity and the junction leakage current have been evaluated in the device reliability point of view, and it is confirmed that there are no problems to use this technique in STI technology.
Keywords
MOSFET; annealing; diffusion; isolation technology; leakage currents; oxidation; NO-annealed wall oxidation; Si:B-SiO; device reliability; gate oxide integrity; inverse narrow width effect; junction leakage current; n-MOST; p-MOST; shallow trench isolation; Boron; Controllability; Etching; Impurities; Isolation technology; Leakage current; Oxidation; Silicon; Threshold voltage;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.887470
Filename
887470
Link To Document