An asymmetrical lightly doped drain (LDD) self-aligned gate heterostructure field effect transistor

An asymmetrical LDD structure next to the gate was used to improve the breakdown voltages and short-channel characteristics (such as subthreshold currents, threshold voltage uniformity, and output conductance) of self-aligned gate heterostructure FETs (HFETs). This approach decreases impact ionization and increases the breakdown voltage. Previous approaches have created symmetrical lightly doped regions around the gate by using a sidewall spacer, which resulted in high source resistances and transconductance degradation, leading to a tradeoff in transconductance and breakdown voltage. In the LDD HFET, drain-to-source breakdown voltage increased from 4.5 to 12 V and drain-to-gate breakdown voltage improved from 8.8 to 25 V, while the transconductance remained unchanged at 250 mS/mm, as the length of the lightly doped region is varied from 0 to 1 μm. Experimental data show that the LDD structure eliminates threshold voltage roll off and improves V_T uniformity across a 3-in. wafer at gate lengths of 0.55 μm. Further analysis of the subthreshold characteristics and the threshold voltage sensitivity to drain bias shows that the LDD HFET is much less sensitive to drain bias than the conventional HFET