• DocumentCode
    1414630
  • Title

    Modified super pass gate for multiple-valued logic circuits

  • Author

    Kelly, P.M. ; McGinnity, T.M. ; Maguire, L.P.

  • Author_Institution
    Intelligent Syst. Eng. Lab., Ulster Univ., Londonderry, UK
  • Volume
    36
  • Issue
    22
  • fYear
    2000
  • fDate
    10/26/2000 12:00:00 AM
  • Firstpage
    1834
  • Lastpage
    1836
  • Abstract
    A model of a super pass gate (SPG) is adapted to allow multiple-valued logic circuit connections and designs that are normally prohibited by the formal synthesis and minimisation technique for the device. The modification of the SPG allows more efficient circuit minimisation to be achieved for functions that do not readily reduce under the formal synthesis technique
  • Keywords
    multivalued logic circuits; MVL circuits; circuit minimisation; modified super pass gate; multiple-valued logic circuits;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20001288
  • Filename
    888417
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1414630