• DocumentCode
    1415741
  • Title

    Improving threshold-voltage uniformity of 0.1 μm InP-based MODFETs with different gate layouts

  • Author

    Xu, D. ; Enoki, T. ; Suemitsu, T. ; Umeda, Y. ; Yamane, Y. ; Ishii, Y.

  • Author_Institution
    NTT Syst. Electron. Lab., Kanagawa, Japan
  • Volume
    34
  • Issue
    16
  • fYear
    1998
  • fDate
    8/6/1998 12:00:00 AM
  • Firstpage
    1614
  • Lastpage
    1615
  • Abstract
    It is shown that the threshold-voltage uniformity of 0.1 μm InAlAs/InGaAs-based modulation-doped field-effect transistors with different numbers of gate fingers and different gate widths can be improved when a thin cap-layer structure is employed. This improvement is based on the reduction of the recess time. This reduction suppresses the difference in etching that results from the different etching rates caused by the different electrochemical effects that occur because of the varied gate layouts
  • Keywords
    III-V semiconductors; etching; high electron mobility transistors; indium compounds; 0.1 micron; InP; InP MODFET; cap layer; electrochemical etching; gate layout; recess time; threshold voltage uniformity;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19981118
  • Filename
    707175
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1415741