DocumentCode
1415873
Title
Multiple twisted data line technique for scaled DRAMs
Author
Min, Dong-Sun ; Langer, D.W. ; Kim, Gyu-Hyun
Author_Institution
Dept. of Electr. Eng., Pittsburgh Univ., PA, USA
Volume
34
Issue
13
fYear
1998
fDate
6/25/1998 12:00:00 AM
Firstpage
1296
Lastpage
1297
Abstract
A new multiple twisted data line technique to reduce both bit-line and word-line coupling noises is proposed and demonstrated. An improved noise/signal ratio resulting from the application of the proposed technique is confirmed by soft-error rate tests. A faster data access time can also be expected when the proposed technique is incorporated into dynamic random access memories
Keywords
DRAM chips; integrated circuit noise; bit-line coupling noise; data access time; dynamic random access memory; multiple twisted data line; noise/signal ratio; scaled DRAM; soft-error rate; word-line coupling noise;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19980933
Filename
707197
Link To Document