A Low Overhead Last-Write-Touch Prediction Scheme

Last-write-touch prediction can reduce cache-to-cache transfer latency by converting 3-hop misses into 2-hop misses in directory-based shared-memory multiprocessors. By predicting a last-write-touch and self-downgrading a cache block in advance, a processor can get the data from the memory directly and the coherence overhead is significantly reduced. In this paper, we propose a new low overhead last-write-touch prediction scheme that exploits the inherent write burst characteristics of programs. The scheme uses write burst numbers to compute history traces and generate signatures. Compared with the existing instruction-based prediction technique, much storage overhead can be reduced. The experimental results show that our last-write-touch prediction scheme can achieve almost the same prediction accuracy as the instruction-based prediction scheme with the storage overheads of the history table reduced by 69% and the storage overheads of the signature table reduced by 36%.