New System-in-Package (SiP) Integration technologies

Author

Yu, Doug C. H.

Author_Institution

R&D, Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan

fYear

2014

fDate

15-17 Sept. 2014

Firstpage

1

Lastpage

6

Abstract

New System-in-Package (SiP) with innovative Wafer-Level-System-Integration (WLSI) technologies that leverage foundry core competence on wafer processes have been demonstrated. The WLSI technologies include Chip-on-Wafer-on-Substrate (CoWoS^TM) 3DIC and interposer, Integrated Fan-Out (InFO) and Chip-Scale Wafer-Level-Packaging. Wide application portfolio from very low I/O pin-count, low-cost devices, to medium, high and ultra-high pin-count are realized. Chip-partition followed by flexible powerful integration of single-chip or multi-chips, advanced or matured Si, logic and memory, SoC and sensor/MEMS. System values include low profile, low power, high bandwidth along with competitive cost can be readily achieved. With the chip-partition, we can sustain Moore´s law longer.

Keywords

chip scale packaging; system-in-package; three-dimensional integrated circuits; wafer level packaging; 3DIC; WLSI technologies; chip on wafer on substrate; chip partition; chip scale wafer level packaging; foundry core competence; innovative wafer level system integration technologies; integrated fan out; interposer; system in package integration technologies; wafer processes; Foundries; Packaging; Radio frequency; Silicon; Stacking; System-on-chip; Three-dimensional displays; 3DIC; CoWoS; InFO; Interposer; Moore´s law; System-in-Package (SiP); TSV; chip partition; fan-in; fan-out; wafer level system integration (WLSI);

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2014.6946001

Filename

6946001