Machine learning-based VLSI cells shape function estimation

We describe in this paper a novel approach based upon machine learning for estimating layout shape functions of full-custom integrated circuit cells. A neural network is trained to estimate one dimension of cell layout from circuit netlist, a desired packing density, and prescribed values of the complementary dimension. The neural network is then combined with a linear function generator and a neural network that predicts the number of contacts (vias) to produce estimates of cell layout shape functions. We have experimented with this approach on an independent test set of circuits and the results are very encouraging. The resulting estimation system is very fast and can be easily incorporated into exiting floorplanning systems. An additional benefit of the the machine learning aspect is the simplicity and systematicity in incorporating into the estimation system new circuits and technology information as they become available