DocumentCode
141920
Title
POWER8 design methodology innovations for improving productivity and reducing power
Author
Ziegler, M.M. ; Puri, R. ; Philhower, Bob ; Franch, Robert ; Luk, Wayne ; Leenstra, J. ; Verwegen, Peter ; Fricke, Niels ; Gristede, George ; Fluhr, E. ; Zyuban, V.
Author_Institution
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
2014
fDate
15-17 Sept. 2014
Firstpage
1
Lastpage
9
Abstract
The design complexity of modern high performance processors calls for innovative design methodologies for achieving time-to-market goals. New design techniques are also needed to curtail power increases that inherently arise from ever increasing performance targets. This paper describes new design approaches employed by the POWER8 processor design team to address complexity and power consumption challenges. Improvements in productivity are attained by leveraging a new and more synthesis-centric design methodology. New optimization strategies for synthesized macros allow power reduction without sacrificing performance. These methodology innovations contributed to the industry leading performance of the POWER8 processor. Overall, POWER8 delivers a 2.5x increase in per-socket performance over its predecessor, POWER7+, while maintaining the same power dissipation.
Keywords
innovation management; integrated circuit design; low-power electronics; microprocessor chips; POWER8 design methodology innovations; high performance processors; innovative design; power dissipation; time to market goals; Complexity theory; Design methodology; IP networks; Latches; Productivity; Program processors; Timing; Design methodology; low power design; processors; servers; synthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
Conference_Location
San Jose, CA
Type
conf
DOI
10.1109/CICC.2014.6946042
Filename
6946042
Link To Document