Elimination of error from fully compelled interregister signalling

The fully compelled signalling sequence is frequently used for interregister signalling in telecommunications. The sequence is reasonably reliable, but erors can be experienced when interruptions arise in the transmission path between registers. The paper examines every possible effect of line interruptions, and produces constraints which enable every source of error to be positively eliminated. The constratints govern the application and setting of the timing circuits which, in one form or anothe, are employed with existing fully compelled signalling equipment. The timing circuits do not have stringent requirements, and a standard setting is applicable to all environments.