Wireline clocking and equalization

State-of-the-art commercial wireline data rates are currently at 25–28Gb/s NRZ over a channel with 30dB loss at Nyquist frequency. Low-jitter clock synthesizers, together with feed-forward equalization (FFE), continuous-time linear equalization (CTLE) and decision feedback equalization (DFE) are key enablers of this technology. The next generation will operate at or above 50Gb/s per lane. Needless to say, even with more forgiving channels, 16nm CMOS, and changes to more exotic modulation formats, quality clocking and equalization will become even more essential to the commercialization of 50Gb/s designs. The five papers in this session address these challenges.