• DocumentCode
    142059
  • Title

    Testability and reliability enhancement techniques

  • Author

    Li, Mike ; Roberts, Gordon

  • Author_Institution
    Altera
  • fYear
    2014
  • fDate
    15-17 Sept. 2014
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    This session presents the latest state-of-art testability and reliability enhancement circuit techniques, including design for testability (DFT) techniques for all-digital phase-locked loop (ADPLL), a low-leakage electrostatic discharge (ESD) clamp integrated circuit (IC), measurement ICs for plasma-induced damage (PID) and random telegraph noise (RTN).
  • Keywords
    Clamps; Discrete Fourier transforms; Frequency measurement; Integrated circuit reliability; Integrated circuits; Temperature measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
  • Conference_Location
    San Jose, CA, USA
  • Type

    conf

  • DOI
    10.1109/CICC.2014.6946114
  • Filename
    6946114
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=142059