A novel implementation approach for an ATM switch with a per-VC architecture

Let S be the set of virtual connection (VC) streams being multiplexed by a statistical multiplexer. A statistical multiplexer is said to be a per-VC multiplexer if, to the ith VC stream, the statistical multiplexer appears as a single server queue with a buffer space ≥ Bi cells and a service time of ≤ Di slots, for each i ∊ S. An N × N ATM switch consists of N statistical multiplexers and is said to have a per-VC architecture if it uses per-VC multiplexers. Such a switch provides several advantages: It enables the network to provide diverse end-to-end Quality of Service (QoS) guarantees to heterogeneous traffic streams on a per-VC basis. Per-VC architecture also enables us to devise efficient flow-control schemes for available bit rate (ABR) VCs. We propose a new ATM switch with a per-VC architecture called the virtual connection queue (VCQ) ATM switch. We also propose a connectionist implementation of the VCQ ATM which implements all functions in hardware and which avoids the use of any central processors. A connectionist implementation of a system is comprised of a large number of simple processing/storage elements (PSEs) interconnected to form a cooperative parallelism.