• DocumentCode
    1423172
  • Title

    A compositional model for the functional verification of high-level synthesis results

  • Author

    Borrione, Dominique ; Dushina, Julia ; Pierre, Laurence

  • Author_Institution
    TIMA, Grenoble, France
  • Volume
    8
  • Issue
    5
  • fYear
    2000
  • Firstpage
    526
  • Lastpage
    530
  • Abstract
    High-level synthesis systems, such as Amical, translate a behavioral description to an abstract automaton in which the states are decision and synchronization points, and operations are executed on the state transitions. After the scheduling and allocation of the functional units, the system is modeled as the interconnection of an operative and a control part. To formally verify this synthesis mechanism, we combine a detailed state encoding of the control part with an abstract view of the data part. We only compute the set of reachable states of the control part, and compose functional expressions in the data part. We show that, for each of two corresponding state transitions in the abstract automaton and in the synthesized control part, the expressions computed in the data registers and outputs are equal.
  • Keywords
    formal verification; graph theory; high level synthesis; scheduling; Amical; abstract automaton; allocation; behavioral description; compositional model; data registers; detailed state encoding; functional expressions; functional verification; high-level synthesis results; reachable states; scheduling; state transitions; synchronization points; Automata; Automatic control; Control system synthesis; Encoding; High level synthesis; Integrated circuit interconnections; Libraries; Logic design; Processor scheduling; Registers;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/92.894157
  • Filename
    894157