• DocumentCode
    1423522
  • Title

    Efficient back-bias voltage generator with suppressed parasitic bipolar action for low voltage DRAMs

  • Author

    Min, Kyeong-Sik

  • Author_Institution
    Advanced DRAM Design Dept., Hyundai Electron. Ind. Co. Ltd., Cheongju, South Korea
  • Volume
    37
  • Issue
    1
  • fYear
    2001
  • fDate
    1/4/2001 12:00:00 AM
  • Firstpage
    6
  • Lastpage
    8
  • Abstract
    A high-efficiency back-bias voltage generator with a cross-coupled hybrid pumping circuit (CHPC2) is presented. This scheme suppresses the parasitic bipolar turning-on so as not to lose the pumping current into the parasitic n-p-n bipolar transistor. The proposed generator exhibits better efficiency and faster pumping speed compared with previous bipolar-suppressed back-bias voltage generators
  • Keywords
    CMOS memory circuits; DRAM chips; low-power electronics; LV dynamic RAM; back-bias voltage generator; cross-coupled hybrid pumping circuit; high-efficiency voltage generator; low voltage DRAMs; parasitic bipolar action suppression; parasitic n-p-n bipolar transistor;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20010047
  • Filename
    894330
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1423522