• DocumentCode
    1424254
  • Title

    Power-/energy-efficient BIST schemes for processor data paths

  • Author

    Kranitis, Nektarios ; Gizopoulos, Dimitris ; Paschalis, Antonis ; Psarakis, Mihalis ; Zorian, Yervant

  • Author_Institution
    NCSR Demokritos, Greece
  • Volume
    17
  • Issue
    4
  • fYear
    2000
  • Firstpage
    15
  • Lastpage
    28
  • Abstract
    Processor core power is primarily consumed in a data path consisting of high-activity functional modules. We propose low-power/energy BIST schemes for data path architectures built around the most common combinations of multipliers, adders, ALUs, and shifters
  • Keywords
    built-in self test; logic design; logic testing; BIST; BIST schemes; data path architectures; low-power; processor data paths; Adders; Batteries; Built-in self-test; Circuit testing; Energy consumption; Energy efficiency; Failure analysis; Packaging; Power system reliability; Test pattern generators;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.895003
  • Filename
    895003
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1424254