DocumentCode
1424965
Title
Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering
Author
Das, Debasish ; Killpack, Kip ; Kashyap, Chandramouli ; Jas, Abhijit ; Zhou, Hai
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
Volume
29
Issue
3
fYear
2010
fDate
3/1/2010 12:00:00 AM
Firstpage
466
Lastpage
478
Abstract
With continued scaling of technology into nanometer regimes, the impact of coupling induced delay variations is significant. While several coupling-aware static timers have been proposed, the results are often pessimistic with many false failures. We present an integrated iterative timing filtering and logic filtering based approach to reduce pessimism. We use a realistic coupling model based on arrival times and slews, and show that non-iterative pessimism reduction algorithms proposed in previous research may give potentially non-conservative timing results. On a functional block from an industrial 65 nm microprocessor, our algorithm produced a maximum pessimism reduction of 11.18% of cycle time over converged timing filtering analysis that does not consider logic constraints.
Keywords
integrated circuit modelling; iterative methods; microprocessor chips; nanoelectronics; statistical analysis; timing circuits; coupling-aware static timing analysis; iterative logic filtering; iterative timing filtering; microprocessor; pessimism reduction; Capacitance; Delay; Filtering; Iterative algorithms; Iterative methods; Logic; Microprocessors; Switches; Timing; Wires; Interconnect; SAT; physical design; signal integrity; timing analysis; timing verification;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2009.2035532
Filename
5419240
Link To Document