Design and Implementation of an Arithmetic Processor Unit Based on the Logarithmic Number System

This paper presents the design and implementation of an arithmetic processing unit based on the logarithmic number system. The proposed implementation is supported in a new set of linear equations, which allows calculating the approximation of the logarithm and antilogarithm binary functions and leads to a maximum relative error of 1×10^-3% and 5×10^-3%, respectively. Furthermore, the impact of the logarithmic number system on FPGA for implementing hardware modules to execute multiplication, division, and square root arithmetic operations is also presented and analyzed. In this regards, the analysis takes into account physical resources available on the FPGA, number of clock cycles per arithmetic operation and maximum clock frequency. Experimental results show that using the proposed architecture implemented on the FPGA allows computing multiplication, division and square root operations in only 2 cycles and up to 290.87MHz, obtaining a maximum relative error of 0.015%, 0.018%, and 0.008%, respectively for each one of these arithmetic operations.