• DocumentCode
    1427816
  • Title

    Rapid failure analysis using contamination-defect-fault (CDF) simulation

  • Author

    Khare, Jitendra ; Maly, Wojciech

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
  • Volume
    9
  • Issue
    4
  • fYear
    1996
  • fDate
    11/1/1996 12:00:00 AM
  • Firstpage
    518
  • Lastpage
    526
  • Abstract
    This paper describes a new methodology for rapid failure analysis. The methodology is based on the contamination defect-fault (CDF) simulator CODEF, which is able to map the effects of contamination deposited on an IC cell during any stage of the manufacturing process, onto circuit-level faults. The utilization of CODEF´s capabilities-in both single contamination mode and Monte Carlo mode-in speeding up failure analysis is illustrated in the paper with examples
  • Keywords
    Monte Carlo methods; VLSI; circuit analysis computing; digital simulation; economics; failure analysis; fault diagnosis; integrated circuit manufacture; integrated circuit reliability; integrated circuit yield; CODEF; IC cell; IC yield; Monte Carlo mode; VLSI; circuit-level faults; contamination-defect-fault simulation; rapid failure analysis; single contamination mode; Analytical models; Circuit faults; Circuit simulation; Contamination; Costs; Fabrication; Failure analysis; Investments; Manufacturing processes; Transistors;
  • fLanguage
    English
  • Journal_Title
    Semiconductor Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0894-6507
  • Type

    jour

  • DOI
    10.1109/66.542167
  • Filename
    542167
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1427816