A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

Author

Yoo, Jei-Hwan ; Kim, Chang-Hyun ; Lee, Kyu-Chan ; Kyung, Kye-Hyun ; Yoo, Seung-Moon ; Lee, Jung-Hwa ; Son, Moon-Hae ; Jin-Man ; Kang, Bok-Moon ; Ejaz Haq ; Lee, Sang-Bo ; Sim, Jai-Hoom ; Kim, Joung-Woo ; Moon, Byung-Ski ; Kim, Keum-Young ; Park, Jae-Gwan

Author_Institution

Memory Div., Samsung Electron. Co., Kyungid-Do, South Korea

Volume

31

Issue

11

fYear

1996

fDate

11/1/1996 12:00:00 AM

Firstpage

1635

Lastpage

1644

Abstract

This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V _cc=2.0 V and 25°C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single I/O line driving write scheme to reduce power consumption; (3) a self-strobing I/O schemes to achieve high bandwidth with low power dissipation; and (4) a block redundancy scheme with increased flexibility. The nonstitched chip with an area of 652 mm ² has been fabricated using 0.16 μm four-poly, four-metal CMOS process technology

Keywords

CMOS memory circuits; DRAM chips; memory architecture; redundancy; 0.16 micron; 1 Gbit; 2 V; 31 ns; CMOS IC; block redundancy scheme; four-poly four-metal process technology; high bandwidth; low power dissipation; merged multibank architecture; nonstitched chip; self-strobing I/O schemes; self-strobing synchronous DRAM; Bandwidth; CMOS process; CMOS technology; Circuits; Clocks; Delay; Energy consumption; Frequency; Moon; Multiprocessing systems; Power dissipation; Random access memory; Registers;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1996.542308

Filename

542308