• DocumentCode
    1430528
  • Title

    A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay

  • Author

    Saek, Takanoro ; Nakaoka, Yuji ; Fujita, Mamoru ; Tanaka, Akihito ; Nagata, Kyoichi ; Sakakibara, Kenichi ; Matano, Tatsuya ; Hoshino, Yukio ; Miyano, Kazutaka ; Isa, Satoshi ; Nakazawa, Shigeyuki ; Kakehashi, Eiichiro ; Drynan, John Mark ; Komuro, Masahi

  • Author_Institution
    NEC Corp., Sagamihara, Japan
  • Volume
    31
  • Issue
    11
  • fYear
    1996
  • fDate
    11/1/1996 12:00:00 AM
  • Firstpage
    1656
  • Lastpage
    1668
  • Abstract
    A 256-Mb SDRAM (245.7 mm2) has been developed using (1) a high cell occupation ratio (60.2%) array design for chip size reduction and a high yield, (2) a prefetched pipeline scheme (PPS) using a first-in first-out (FIFO) buffer with parallel serial converter for 250-MHz clock frequency operation, and (3) a synchronous mirror delay (SMD) circuit for 2.5-ns clock access and low standby current
  • Keywords
    DRAM chips; delay circuits; 2.5 ns; 250 MHz; 256 Mbit; FIFO buffer; SDRAM; array design; cell occupation ratio; chip size; clock access; parallel serial converter; prefetched pipeline scheme; standby current; synchronous mirror delay circuit; yield; Circuits; Clocks; Delay; Frequency conversion; Mirrors; Phase locked loops; Pipelines; Prefetching; Random access memory; SDRAM; Systolic arrays;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1996.542310
  • Filename
    542310
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1430528