EDA challenges facing future microprocessor design

Author

Karn, T. ; Rawat, Shishpal ; Kirkpatrick, Desmond ; Roy, Rabindra ; Spirakis, Gregory S. ; Sherwani, Naveed ; Peterson, Craig

Author_Institution

Intel Corp., Hillsboro, OR, USA

Volume

19

Issue

12

fYear

2000

fDate

12/1/2000 12:00:00 AM

Firstpage

1498

Lastpage

1506

Abstract

As microprocessor design progresses from tens of millions of transistors on a chip using 0.18-μm process technology to approximately a billion transistors on a chip using 0.10-μm and finer process technologies, the microprocessor designer faces unprecedented Electronic Design Automation (EDA) challenges over the future generations of microprocessors. This paper describes the changes in the design environment that will be necessary to develop increasingly complex microprocessors. In particular, the paper describes the current status and the future challenges along three important areas in a design flow: design correctness, performance verification and power management

Keywords

VLSI; circuit CAD; formal verification; integrated circuit design; low-power electronics; microprocessor chips; 0.1 to 0.18 micron; EDA challenges; complex microprocessors; design correctness; design environment; electronic design automation; microprocessor design; performance verification; power management; Clocks; Design methodology; Electronic design automation and methodology; Energy management; Hardware design languages; Microprocessors; Power dissipation; Production; Silicon; Transistors;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.898828

Filename

898828