DocumentCode
1433790
Title
An algorithmic 15-bit CMOS digital-to-analog converter
Author
Pelgrom, Marcel J M ; Roorda, Mauricio
Author_Institution
Philips Res. Labs., Eindhoven, Netherlands
Volume
23
Issue
6
fYear
1988
fDate
12/1/1988 12:00:00 AM
Firstpage
1402
Lastpage
1405
Abstract
A digital-to-analog converter (DAC) has been designed which uses an algorithm based on interpolation. The algorithm ensures monotonicity and differential linearity despite offset voltages, and hence eliminates the need for trimming. The technique has been used to design a 15-bit DAC in a 2.5-μm CMOS technology. The converter features S/(N+THD) of 74 dB with a dynamic range of 87 dB and a power consumption of 22 mW at 44-kHz sample frequency
Keywords
CMOS integrated circuits; circuit CAD; digital-analogue conversion; interpolation; 15 bit; 15-bit CMOS digital-to-analog converter; 2.5 micron; 22 mW; 44 kHz; differential linearity; interpolation; monotonicity; Algorithm design and analysis; CMOS technology; Capacitors; Clocks; Digital-analog conversion; Dynamic range; Energy consumption; Interpolation; Linearity; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.90037
Filename
90037
Link To Document