Gate-Side and Substrate-Side Oxide Trap and Interface State Generation in Conventional and Nitrided Tunnel Oxides of Floating Gate Cells

We present the investigation of the generation of oxide traps near the gate, near the substrate, and at the oxide/substrate interface (interface states) in conventional furnace and nitrided tunnel oxides of floating gate (FG) memory cells. The trap densities at these three locations, together with information about fixed oxide charges, were obtained by a measurement technique combining transient stress-induced leakage current and transient capacitance measurements, and by capacitance-voltage methods. The degradation behavior of 8.5-nm state-of-the-art tunnel oxides under Fowler-Nordheim current stress was investigated for both stress polarities and correlated to the endurance characteristics of FG electrically erasable programmable read-only memory cells with identical tunnel oxides. Because of this, it is possible for the first time to localize the oxide region of nitrided tunnel oxides responsible for the well-known endurance improvement compared to conventional furnace tunnel oxides. Furthermore, possible degradation mechanisms resulting in the observed local trap densities are discussed.