DocumentCode
1434363
Title
A 512 16-b bit-serial sorter chip
Author
Afghahi, M.
Author_Institution
LSI Design Center, Linkoping Univ., Sweden
Volume
26
Issue
10
fYear
1991
fDate
10/1/1991 12:00:00 AM
Firstpage
1452
Lastpage
1457
Abstract
A hardware algorithm is presented for sorting. This algorithm is based on a highly pipelined bit-serial architecture. The processing time of this sorter is linearly proportional to the number of data. Sorting cells are much smaller and simpler than previously reported sorter cells. A single chip sorting 512 16-b keys was designed with a 2-μm process and simulated at 240 MHz. For sorting sequences up to 512 keys along, the performance of this sorter is more than 60 times better than previously reported hardware sorters
Keywords
VLSI; microprocessor chips; parallel architectures; pipeline processing; sorting; 2 micron; VLSI; bit-serial sorter chip; hardware algorithm; highly pipelined bit-serial architecture; processing time; sorting; sorting sequences; Circuits; Clocks; Costs; Engines; Hardware; Multiplexing; Parallel algorithms; Shift registers; Sorting; Very large scale integration;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.90101
Filename
90101
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