One-chip wonders

Author

McShane, Erik ; Trivedi, Malay ; XU, Ying ; Khandelwal, Pankaj ; Mulay, Amit ; Shenai, Krishna

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Illinois Univ., Chicago, IL, USA

Volume

14

Issue

5

fYear

1998

fDate

9/1/1998 12:00:00 AM

Firstpage

35

Lastpage

42

Abstract

Consumer demand for portable computing and mobile wireless communications will continue to drive development of functionally integrated, ultra-low-power systems on a chip. CMOS bulk processing is likely to emerge as the foundation of mixed-signal, ultra-low-power ICs because of its inherent advantages for low-power logic and flexibility in RF applications. To successfully meet time-to-market goals and shrink product-development cycles, computer-aided design tools must guide a design from conceptualization to physical implementation. Estimates of floorplan arrangement and interconnect and package parasitics are necessary early in the design flow, since these undesirable contributions can dominate over the intrinsic device parasitics

Keywords

CMOS integrated circuits; circuit CAD; integrated circuit design; mixed analogue-digital integrated circuits; CMOS bulk processing; RF architecture; computer aided design; floorplan; interconnect parasitics; mixed-signal IC; package parasitics; single chip integration; ultra-low-power system; Application software; CMOS logic circuits; CMOS process; Design automation; Mobile computing; Packaging; Portable computers; Radio frequency; Time to market; Wireless communication;

fLanguage

English

Journal_Title

Circuits and Devices Magazine, IEEE

Publisher

ieee

ISSN

8755-3996

Type

jour

DOI

10.1109/101.721518

Filename

721518