Review of high-speed addition techniques

A new large computing machine, the MU5, is under construction at Manchester University. As one aspect of the design of this machine, a review of available addition techniques was undertaken. This included both the use of special circuits for improving carry-propagation speeds, and the effects of restricted fan out and fan in on logical adders. The fastest adder uses a combination of block-carry and conditional-sum approaches and may be further improved by use of the sequential-state technique; emitter-coupled logic being used. Where economy is more important than speed, transistor-transistor medium-scale-integrated logic had advantages. Other techniques discussed include the saturated-transistor carry-path and serial-parallel adders.