• DocumentCode
    1439080
  • Title

    A delay model for router microarchitectures

  • Author

    Peh, Li-Shiuan ; Dally, William J.

  • Author_Institution
    Stanford Univ., CA, USA
  • Volume
    21
  • Issue
    1
  • fYear
    2001
  • Firstpage
    26
  • Lastpage
    34
  • Abstract
    This article introduces a router delay model that takes into account the pipelined nature of contemporary routers and proposes pipelines matched to the specific flow control method employed. Given the type of flow control and router parameters, the model returns router latency in technology-independent units and the number of pipeline stages as a function of cycle time. We apply this model to derive realistic pipelines for wormhole and virtual-channel routers and compare their performance. Contrary to the conclusions of previous models, our results show that the latency of a virtual channel router doesn´t increase as we scale the number of virtual channels up to 8 per physical channel. Our simulation results also show that a virtual-channel router gains throughput of up to 40 % over a wormhole router
  • Keywords
    computer architecture; multiprocessor interconnection networks; network routing; cycle time; delay model; performance; pipelined nature; router latency; router microarchitectures; simulation results; technology-independent units; virtual channels; virtual-channel routers; wormhole; wormhole router; Clocks; Communication switching; Delay; Fabrics; Microarchitecture; Multiprocessor interconnection networks; Pipeline processing; Routing; Semiconductor device modeling; Switches;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/40.903059
  • Filename
    903059