A Task-Centric Memory Model for Scalable Accelerator Architectures

Author

Kelm, John H. ; Johnson, Daniel R. ; Lumetta, Steven S. ; Patel, Sanjay J. ; Frank, Matthew I.

Author_Institution

Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA

Volume

30

Issue

1

fYear

2010

Firstpage

29

Lastpage

39

Abstract

This article presents a memory model for parallel compute accelerators with task-based programming models that uses a software protocol, working in collaboration with hardware caches, to maintain a coherent, single address space view of memory without requiring hardware cache coherence. The memory model supports visual computing applications, which are becoming an important class of workloads capable of exploiting 1,000-core processors.

Keywords

memory architecture; microprocessor chips; multiprocessing systems; parallel programming; protocols; task analysis; core processors; general-purpose chip multiprocessor; hardware cache coherence; scalable accelerator architectures; software protocol; task-based programming models; task-centric memory model; visual computing; Accelerator architectures; Coherence; Collaborative software; Collaborative work; Computer applications; Concurrent computing; Hardware; Parallel programming; Protocols; Software maintenance; accelerator; memory model; parallel architecture; software coherence;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/MM.2010.6

Filename

5430737