DocumentCode
1439678
Title
Making Address-Correlated Prefetching Practical
Author
Wenisch, Thomas F. ; Ferdman, Michael ; Ailamaki, Anastasia ; Falsafi, Babak ; Moshovos, Andreas
Author_Institution
Univ. of Michigan, Ann Arbor, MI, USA
Volume
30
Issue
1
fYear
2010
Firstpage
50
Lastpage
59
Abstract
Despite a decade of research demonstrating its efficacy, address-correlated prefetching has never been implemented in a shipping processor because it requires megabytes of metadata - too large to store practically on chip. New storage-, latency-, and bandwidth-efficient mechanisms for storing metadata off chip yield a practical design that achieves 90 percent of the performance potential of idealized on-chip metadata storage.
Keywords
meta data; storage management; storage management chips; address correlated prefetching; bandwidth efficient mechanisms; latency efficient mechanisms; on-chip metadata storage; shipping processor; storage efficient mechanisms; Bandwidth; Delay; Hardware; Innovation management; Prefetching; Production; System-on-a-chip; Table lookup; Technological innovation; Throughput; address-correlated prefetching; cache memories;
fLanguage
English
Journal_Title
Micro, IEEE
Publisher
ieee
ISSN
0272-1732
Type
jour
DOI
10.1109/MM.2010.21
Filename
5430739
Link To Document