Guest Editors´ Introduction: Compact Variability Modeling in Scaled CMOS Design

As CMOS technology is scaled down into the nanometer range, variation control becomes much more challenging, having a fundamental impact on all aspects of IC design. Although continual improvements in manufacturing processes are mitigating some of variability\´s negative effects, the semiconductor industry is starting to accept that some effects are better mitigated during the design phase. Handling variability in the design step will require accurate, consistent models of variability and its dependence on designable parameters, and of variability\´s spatial and temporal distributions. Such models are quite different from the "corner" models deployed thus far to model manufacturing variability. Consequently, the compact modeling of systematic, spatial, and random variations is essential to abstract the physical-level variations into a format that designers can use.